View S6B0725A_7697079.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

contents in this document are subject to change without notice. no part of this document may be reproduced or transmitted in any form or by any means, electro nic or mechanical, for any purpose, without the express written permission of lcd driver ic team. precautions for light light has characteristics to move electrons in the integrated circuitry of semiconductors, therefore may change the characteristics of semiconductor devices when irradiated with light. consequently, the users of the packages which may expose chips to external light such as cob, cog, tcp and cof must consider effective methods to block out light from reaching the ic on all parts of the su rface area, the top, bottom and the sides of the chip. follow the precautions below when using the products. 1. consider and verify the protection of penetrating light to the ic at substrate ( board or glass) or product design stage. 2. always test and inspect p roducts under the environment with no penetration of light. S6B0725A 1 04 seg / 65 com driver & controller for stn lcd aug . 2001 ver . 1.5
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 1.5 S6B0725A 2 S6B0725A specification revision history version content date 0.0 initial v ersion 2000.07 1.0 1. vlcd pin: input or output pin ? only output pin (page 8, 24) 2001. regulator resistor select: (1,1,0), (1,1,1) ? not available (page 27, 38) 2001. vlcd absolute maximum rating: - 0.3v to 15v ? - 0.3v to 13v (page 47) 4. x4 voltage boosting vci range: 2.4v to 3.3v ? 2.4v to 3.0v (page 48) 5. power consumption: tbd valid value 2000.10 1.1 oscillator frequency (f cl ): (typ.) 4.75khz ? 5.45khz (page 48) 2000.11 1.2 vlcd capacitor is greater than 1 m f (page 8, 61) 2001.01 1.3 1. figure 15 is changed (page 27) 2001. figure 2 - 1 , 2 - 2 are added (page 14) 2001. figure 21 is changed (page 43) 4. table 21 is changed (page 50) 5. added detail information for several items 2001.03 1.4 added d ynamic c urrent c onsumption at 4 times boosting operation (page 48) 2001.05 1.5 correct some missp elling s 2001.08
S6B0725A spec . ver. 1.5 104 seg / 65 com driver & controller for stn lcd 3 co ntents introduction ................................ ................................ ................................ ................................ ............ 1 features ................................ ................................ ................................ ................................ .................... 1 block diagram ................................ ................................ ................................ ................................ ......... 3 pad configuration ................................ ................................ ................................ ................................ . 4 pad center coordi nates ................................ ................................ ................................ ...................... 6 pin description ................................ ................................ ................................ ................................ ........ 8 power supply ................................ ................................ ................................ ................................ .... 8 lcd driver supply ................................ ................................ ................................ ............................ 8 system control ................................ ................................ ................................ ................................ 9 microprocessor inter face ................................ ................................ ................................ ......... 10 lcd driver outputs ................................ ................................ ................................ ......................... 12 functional descripti on ................................ ................................ ................................ ....................... 13 microprocessor inter face ................................ ................................ ................................ ......... 13 display data ram (dd ram) ................................ ................................ ................................ .............. 18 lc d display circuits ................................ ................................ ................................ ....................... 21 lcd driver circuits ................................ ................................ ................................ ......................... 23 power supply circuit s ................................ ................................ ................................ .................. 24 reset circuit ................................ ................................ ................................ ................................ .... 30 instruction descript ion ................................ ................................ ................................ ...................... 31 specifications ................................ ................................ ................................ ................................ ......... 46 absolute maximum rat ings ................................ ................................ ................................ ........... 46 dc characteristics ................................ ................................ ................................ ........................ 47 ac characteristics ................................ ................................ ................................ ......................... 50 reference applicatio ns ................................ ................................ ................................ ...................... 54 microprocessor inter face ................................ ................................ ................................ ......... 54 connections between S6B0725A and lcd pan el ................................ ................................ ....... 56

S6B0725A spec . ver. 1.5 104 seg / 65 com driver & controller for stn lcd 1 introduction the S6B0725A is a single - chip driver & controller lsi for graphic dot - matrix liquid cryst al display systems. this chip can be connected directly to a microprocessor, accepts serial or 8 - bit parallel display data from the microprocessor, stores the display data in an on - chip display data ram of 65 x 1 04 bits and generates a liquid crystal displ ay drive signal independent of the microprocessor . it provides a high - flexible display section due to 1 - to - 1 correspondence between on - chip display data ram bits and lcd panel pixels. it contains 6 5 common driver circuits and 1 04 segment driver circuits, s o that a single chip can drive a 65 x 104 dot display. this chip is able to minimize power consumption because it performs display data ram read/write operation with no external operation clock . in addition, because it contains power supply circuits necess ary to drive liquid crystal, which is a display clock oscillator circuit, high performance voltage converter circuit, high - accuracy voltage regulator circuit, low power consumption voltage divider resistors and op - amp for liquid crystal driver power voltag e, it is possible to make the lowest power consumption display system with the fewest components for high performance portable systems . features display driver output circuits - 6 5 common outputs and 1 04 segment outputs on - chip display data ram - capacity: 65 x 1 04 = 6 , 760 bits - ram bit data ? 1 ? : a dot of display is illuminated - ram bit data ? 0 ? : a dot of display is not illuminated applicable duty ratios d uty ratio applicable lcd bias maximum display area 1/ 6 5 1/ 7 or 1/ 9 6 5 1 04 1/55 1/6 or 1/8 55 104 1/49 1/6 or 1/8 49 104 1/33 1/5 or 1/6 33 104 microprocessor interface - high - speed 8 - bit parallel bi - directional interface with 6800 - series or 8080 - series - spi ( serial peripheral i nterface ) available. (only write operation) various function set - display on / off, set initial display line, set page address, set column address, read status, write/read d isplay data, select segment driver output, reverse display on / off, entire display on / off, select lcd bias, set/reset modify - read, select common driver output, control display power circuit, select internal regulator resistor ratio for vlcd voltage regulation, electronic volume, set static indicator state. - h/w and s/w reset available - static drive circuit equipped internally for indicators with 4 f lashing mode
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 1.5 S6B0725A 2 built - in a nalog c ircuit - on - chip oscillator circuit for display clock - high performance v oltage converter ( with booster ratios of x 3 and x 4) - high accuracy voltage regulator (temperature coefficient: - 0.0 5 0.03 %/ c or external input ) - elec tronic contrast control function (64 steps) - vref = 2.1v 3% (vlcd voltage adjustment voltage) - high performance v oltage follower (v1 to v4 voltage divider resistors and op - amp for increasing drive capacity) operating voltage range - supply voltage (v dd ): 2.4 to 3.6 v - lcd driving voltage (v lcd ): 4. 5 to 9. 0 v low power consumption - operating power: 120 m a t yp ical (c onditions: v dd = 3v, x 3 boosting (vci = v dd ), v0 = 7.6 v, internal power supply on , display o ff and normal mode is selected ) - standby power: 10 m a max imum (d uring power save[s tandby] mode) operating temperatures - wide range of operating temperatures : - 40 to 85 c cmos process package type - gold bumped chip
S6B0725A spec . ver. 1.5 104 seg / 65 com driver & controller for stn lcd 3 block diagram cl frs fr duty0 duty1 v dd v ss hpmb vlcd vr intrs ref vext vci dcdc4b v / c circuit v / r circuit v / f circuit 33 common driver circuits mpu interface (parallel & serial) instruction decoder bus holder column address circuit line addres s circuit page address circuit display data ram 65 x 1 04 = 6 , 76 0 bits display data control circuit display timing generator circuit common output controller circuit db0 db1 db2 db3 db4 db5 db6(sclk) db7(sid) c68 resetb p s rw_wrb e_rdb r s c s2 cs1b coms com63 : com32 seg103 seg102 seg101 : : seg2 seg1 seg0 com31 : com0 coms oscillator 1 04 segment driver circuits 33 common driver circuits i/o buffer status register instruction register figure 1 . block diagram
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 1.5 S6B0725A 4 pad configuration eee eeeeeeeeeeeeeeeeeee - - - - - - - - - - eeeeeeeeeeeeeeeeeee eee y 240 132 241 99 274 98 1 S6B0725A (top view) (0,0) x eeeeeeeeeeeeeeeeeeeeee - - - - - - - - - - eeeeeeeeeeeeeeeeeeeeeee eeee - - - - eeee eeee - - - - eeee 133 figure 2 . S6B0725A chip configuration table 1 . S6B0725A pad dimensions size item pad no. x y unit chip size - 8220 2540 1 to 98 70 99 to 100 70 100 to 132 60 133 to 134 80 134 to 135 194 135 to 238 68 238 to 239 194 239 to 240 80 241 to 273 60 pad pitch 273 to 274 70 1 to 98 42 92 99 102 52 100 to 132 102 32 133 to 134 52 102 135 to 238 32 102 239 to 240 52 102 241 to 273 102 32 bumped pad size ( b ottom ) 274 102 52 bumped pad height a ll pad 1 4 (typ.) m m
S6B0725A spec . ver. 1.5 104 seg / 65 com driver & controller for stn lcd 5 cog align key coordinate ilb align key coordinate (with gold bump *) 30 m m 30 m m 30 m m (-3575, 715) 30 m m 30 m m 30 m m (3507.85, -597.65) 30 m m 30 m m 30 m m 60 m m 30 m m 42 m m 108 m m 42 m m 108 m m 42 m m 108 m m 42 m m 108 m m (-4008, 1162) (4008, 1162) * when designing c og pattern, ito pattern must be prohibited on ilb align key, dummy pads , test pads. if ito pattern is used for routing over th ese area, it can be happened pattern - short through bumped pattern on these area .
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 1.5 S6B0725A 6 pad cent er coordinates table 2 . p ad center coordinates [unit: m m] pad pad pad pad pad pad no. name no. name no. name 1 dummy1 -3390 -1155 51 vci 110 -1155 101 com30 3963 -930 2 frs -3320 -1155 52 vci 180 -1155 102 com29 3963 -870 3 fr -3250 -1155 53 vci 250 -1155 103 com28 3963 -810 4 cl -3180 -1155 54 vci 320 -1155 104 com27 3963 -750 5 test1 -3110 -1155 55 vci 390 -1155 105 com26 3963 -690 6 vdd -3040 -1155 56 vci 460 -1155 106 com25 3963 -630 7 vdd -2970 -1155 57 vci 530 -1155 107 com24 3963 -570 8 vdd -2900 -1155 58 vdd 600 -1155 108 com23 3963 -510 9 vdd -2830 -1155 59 vext 670 -1155 109 com22 3963 -450 10 vdd -2760 -1155 60 vss 740 -1155 110 com21 3963 -390 11 vdd -2690 -1155 61 ref 810 -1155 111 com20 3963 -330 12 vdd -2620 -1155 62 vdd 880 -1155 112 com19 3963 -270 13 vdd -2550 -1155 63 dcdc4b 950 -1155 113 com18 3963 -210 14 vdd -2480 -1155 64 vss 1020 -1155 114 com17 3963 -150 15 vdd -2410 -1155 65 hpmb 1090 -1155 115 com16 3963 -90 16 vdd -2340 -1155 66 vdd 1160 -1155 116 com15 3963 -30 17 vdd -2270 -1155 67 intrs 1230 -1155 117 com14 3963 30 18 vdd -2200 -1155 68 vss 1300 -1155 118 com13 3963 90 19 vdd -2130 -1155 69 vss 1370 -1155 119 com12 3963 150 20 db0 -2060 -1155 70 vss 1440 -1155 120 com11 3963 210 21 db1 -1990 -1155 71 vss 1510 -1155 121 com10 3963 270 22 db2 -1920 -1155 72 vss 1580 -1155 122 com9 3963 330 23 db3 -1850 -1155 73 vss 1650 -1155 123 com8 3963 390 24 db4 -1780 -1155 74 vss 1720 -1155 124 com7 3963 450 25 db5 -1710 -1155 75 vss 1790 -1155 125 com6 3963 510 26 db6 -1640 -1155 76 vss 1860 -1155 126 com5 3963 570 27 db7 -1570 -1155 77 vss 1930 -1155 127 com4 3963 630 28 vss -1500 -1155 78 vr 2000 -1155 128 com3 3963 690 29 test2 -1430 -1155 79 vss 2070 -1155 129 com2 3963 750 30 test3 -1360 -1155 80 testa0 2140 -1155 130 com1 3963 810 31 vss -1290 -1155 81 testb0 2210 -1155 131 com0 3963 870 32 rs -1220 -1155 82 vss 2280 -1155 132 coms 3963 930 33 vdd -1150 -1155 83 vlcd 2350 -1155 133 dummy4 3776 1117 34 duty0 -1080 -1155 84 vlcd 2420 -1155 134 dummy5 3696 1117 35 vss -1010 -1155 85 vlcd 2490 -1155 135 seg0 3502 1117 36 duty1 -940 -1155 86 vlcd 2560 -1155 136 seg1 3434 1117 37 vdd -870 -1155 87 vlcd 2630 -1155 137 seg2 3366 1117 38 ps -800 -1155 88 vlcd 2700 -1155 138 seg3 3298 1117 39 vss -730 -1155 89 testa1 2770 -1155 139 seg4 3230 1117 40 c68 -660 -1155 90 testb1 2840 -1155 140 seg5 3162 1117 41 vdd -590 -1155 91 testa2 2910 -1155 141 seg6 3094 1117 42 e_rdb -520 -1155 92 testb2 2980 -1155 142 seg7 3026 1117 43 rw_wrb -450 -1155 93 testa3 3050 -1155 143 seg8 2958 1117 44 vss -380 -1155 94 testb3 3120 -1155 144 seg9 2890 1117 45 cs1b -310 -1155 95 testa4 3190 -1155 145 seg10 2822 1117 46 cs2 -240 -1155 96 testb4 3260 -1155 146 seg11 2754 1117 47 vdd -170 -1155 97 resetb 3330 -1155 147 seg12 2686 1117 48 vci -100 -1155 98 dummy2 3400 -1155 148 seg13 2618 1117 49 vci -30 -1155 99 dummy3 3963 -1060 149 seg14 2550 1117 50 vci 40 -1155 100 com31 3963 -990 150 seg15 2482 1117 x y x y x y
S6B0725A spec . ver. 1.5 104 seg / 65 com driver & controller for stn lcd 7 table 2 . p ad center coordinates (continued) [unit: m m] pad pad pad pad pad pad no. name no. name no. name 151 seg16 2414 1117 201 seg66 -986 1117 251 com42 -3963 330 152 seg17 2346 1117 202 seg67 -1054 1117 252 com43 -3963 270 153 seg18 2278 1117 203 seg68 -1122 1117 253 com44 -3963 210 154 seg19 2210 1117 204 seg69 -1190 1117 254 com45 -3963 150 155 seg20 2142 1117 205 seg70 -1258 1117 255 com46 -3963 90 156 seg21 2074 1117 206 seg71 -1326 1117 256 com47 -3963 30 157 seg22 2006 1117 207 seg72 -1394 1117 257 com48 -3963 -30 158 seg23 1938 1117 208 seg73 -1462 1117 258 com49 -3963 -90 159 seg24 1870 1117 209 seg74 -1530 1117 259 com50 -3963 -150 160 seg25 1802 1117 210 seg75 -1598 1117 260 com51 -3963 -210 161 seg26 1734 1117 211 seg76 -1666 1117 261 com52 -3963 -270 162 seg27 1666 1117 212 seg77 -1734 1117 262 com53 -3963 -330 163 seg28 1598 1117 213 seg78 -1802 1117 263 com54 -3963 -390 164 seg29 1530 1117 214 seg79 -1870 1117 264 com55 -3963 -450 165 seg30 1462 1117 215 seg80 -1938 1117 265 com56 -3963 -510 166 seg31 1394 1117 216 seg81 -2006 1117 266 com57 -3963 -570 167 seg32 1326 1117 217 seg82 -2074 1117 267 com58 -3963 -630 168 seg33 1258 1117 218 seg83 -2142 1117 268 com59 -3963 -690 169 seg34 1190 1117 219 seg84 -2210 1117 269 com60 -3963 -750 170 seg35 1122 1117 220 seg85 -2278 1117 270 com61 -3963 -810 171 seg36 1054 1117 221 seg86 -2346 1117 271 com62 -3963 -870 172 seg37 986 1117 222 seg87 -2414 1117 272 com63 -3963 -930 173 seg38 918 1117 223 seg88 -2482 1117 273 coms -3963 -990 174 seg39 850 1117 224 seg89 -2550 1117 274 dummy8 -3963 -1060 175 seg40 782 1117 225 seg90 -2618 1117 176 seg41 714 1117 226 seg91 -2686 1117 177 seg42 646 1117 227 seg92 -2754 1117 178 seg43 578 1117 228 seg93 -2822 1117 179 seg44 510 1117 229 seg94 -2890 1117 180 seg45 442 1117 230 seg95 -2958 1117 181 seg46 374 1117 231 seg96 -3026 1117 182 seg47 306 1117 232 seg97 -3094 1117 183 seg48 238 1117 233 seg98 -3162 1117 184 seg49 170 1117 234 seg99 -3230 1117 185 seg50 102 1117 235 seg100 -3298 1117 186 seg51 34 1117 236 seg101 -3366 1117 187 seg52 -34 1117 237 seg102 -3434 1117 188 seg53 -102 1117 238 seg103 -3502 1117 189 seg54 -170 1117 239 dummy6 -3696 1117 190 seg55 -238 1117 240 dummy7 -3776 1117 191 seg56 -306 1117 241 com32 -3963 930 192 seg57 -374 1117 242 com33 -3963 870 193 seg58 -442 1117 243 com34 -3963 810 194 seg59 -510 1117 244 com35 -3963 750 195 seg60 -578 1117 245 com36 -3963 690 196 seg61 -646 1117 246 com37 -3963 630 197 seg62 -714 1117 247 com38 -3963 570 198 seg63 -782 1117 248 com39 -3963 510 199 seg64 -850 1117 249 com40 -3963 450 200 seg65 -918 1117 250 com41 -3963 390 x y x y x y
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 1.5 S6B0725A 8 pin description power supply table 3. power supply pins description name i/o description vdd supply power supply v ss supply ground lcd driver supply table 4. lcd driver supply pins descrip tion name i/o description v lcd o lcd power supply output pin connect this pin to v ss through capacitor.(capacitor is greater than 1 m f) dcdc4b i 4 times boosting circuit enable input pin - dcdc4b = " h ": 3 times boosting - dcdc4b = " l ": 4 times boosting vr i v lcd voltage adjustment pin it is valid only when internal voltage regulator resistors are not used (intrs = ?l?) . vci i this is the reference voltage for the voltage converter circuit for the lcd driving. whether internal voltage converter use or n ot use, this pin should be fixed. the voltage should have the following range: 2.4v vci 3.6v vext i this is the external - input reference voltage (v ref ) for the internal voltage regulator. it is valid only when external v ref is used ( ref = ?l?) . when using internal v ref, this pin is open ref i select the external v ref voltage via vext pin - ref = " l ": u sing the external v ref - ref = " h ": u sing the internal v ref
S6B0725A spec . ver. 1.5 104 seg / 65 com driver & controller for stn lcd 9 system control table 5. system control pins description name i/o description cl o displa y clock output pin frs o static driver segment output pin this pin is used together with the fr pin. fr o static driver common output pin this pin is used together with the frs pin. intrs i internal resistor select pin this pin selects the resistors for adjusting v lcd voltage level. - intrs = ?h?: the internal resistors are used - intrs = ?l?: the external resistors are used v lcd voltage is controlled by vr pin and external resistive divider. (* refer to page 28) the lcd driver duty ratio depends on the following table . duty1 duty0 duty r atio l l 1/33 l h 1/49 h l 1/55 h h 1/65 duty0 duty1 i hpm b i power control pin of the power supply circuit s for lcd driver. - hpm b = ? h ?: normal m ode - hpm b = ? l ?: high power mode
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 1.5 S6B0725A 10 microprocessor inter face table 6. microprocessor i nterface pins description name i/o description resetb i reset input pin when resetb is ?l?, initialization is executed. parallel / serial data input select input ps interface mode chip s elect data / instruction data read / write serial clock h parallel cs1b, cs2 rs db0 to db7 e_rdb rw_wrb - l serial cs1b, cs2 rs sid (db7) write only sclk (db6) ps i *note: in serial mode , it is impossible to read data from th e on - chip ram. and db0 to db5 are high impedance and e_rdb and rw_wrb must be fixed to either ?h? or ?l?. c68 i microprocessor interface select input pin - ps = ? h ? , c68 = "h": 6800 - series parallel mpu interface - ps = ? h ? , c68 = "l": 8080 - series pa rallel mpu interface - ps = ? l ? , c68 = "h": 4 pin - spi serial mpu interface - ps = ? l ? , c68 = "l": 3 pin - spi serial mpu interface cs1b cs2 i chip select input pins data/instruction i/o is enabled only when cs1b is ?l? and cs2 is ?h?. when chip select is no n - active, db0 to db7 may be high impedance. rs i register select input pin - rs = "h": db0 to db7 are display dat a - rs = "l": db0 to db7 are control data * this pin must be fixed to either ? h ? or ? l ? in case of 3 pin - spi serial mpu interface mode read / write execution control pin c68 mpu type rw_wrb description h 6800 - series rw read / write control input pin - rw = ?h?: read - rw = ?l?: write l 8080 - series /wr write enable clock input pin the data on db0 to db7 are latched at the risi ng edge of the /wr signal. rw_wr b i
S6B0725A spec . ver. 1.5 104 seg / 65 com driver & controller for stn lcd 11 table 6. microprocessor interface pins description (continued) name i/o description read / write execution control pin c68 mpu type e_rdb description h 6800 - series e read/write control input pin - rw = ?h?: w hen e is ?h?, db0 to db7 are in an output status. - rw = ?l?: the data on db0 to db7 are latched at the falling edge of the e signal. l 8080 - series /rd read enable clock input pin when /rd is ?l?, db0 to db7 are in an output status. e_rdb i db0 to db7 i/o 8 - bit bi - directional data bus that is connected to the standard 8 - bit microprocessor data bus. when the serial interface selected (ps = "l"), - db0 to db5: high impedance - db6: serial input clock (sclk) - db7: se rial input data (sid) when chip select is not active, db0 to db7 may be high impedance. tests i/o these are pins for chip test. they are set to open. note: dummys ? these pins should be opened (floated).
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 1.5 S6B0725A 12 lcd driver outp uts table 7. lcd driver output pins description name i/o description lcd segment driver outputs the display data and the fr signal control the output voltage of segment driver. segment driver output voltage display data fr normal display reverse display h h v lcd v2 h l v ss v3 l h v2 v lcd l l v3 v ss power save mode v ss v ss seg 0 to seg 103 o lcd common driver outputs the internal scanning data and fr signal control the output voltage of common driver. scan data fr common driver output voltage h h v ss h l v lcd l h v1 l l v4 power save mode v ss com 0 to com 63 o coms o common output for the icons the output signals of two pins are same. when not used, these pins should be left o pen.
S6B0725A spec . ver. 1.5 104 seg / 65 com driver & controller for stn lcd 13 functional descripti on micr oprocessor interface chip select input there are cs1b and cs2 pins for chip selection. the S6B0725A can interface with an mpu only when cs1b is ?l? and cs2 is ?h?. when these pins are set to any other combination, rs, e_rdb, and rw_wrb inputs are disabled and db0 to db7 are to be high impedance. and, in case of serial interface, the internal shift register and the counter are reset. parallel / serial interface S6B0725A has four types of interface with an mpu, which are two serial and two parallel interfaces . this parallel or serial interface is determined by ps pin as shown in table 8 . table 8 . parallel / serial interface mode ps type cs1b cs2 c68 interface mode h 6800 - series mpu mode h parallel cs1b cs2 l 8080 - series mpu mode h 4 p in - spi serial mpu mode l serial cs1b cs2 l 3 pin - spi s erial mpu mode parallel interface (ps = "h") the 8 - bit bi - directional data bus is used in parallel interface and the type of mpu is selected by c68 as shown in table 9 . the type of data transfer is determined by si gnals at rs, e_rdb and rw_wrb as shown in table 10 . table 9 . microprocessor selection for parallel interface c68 cs1b cs2 rs e_rdb rw_wrb db0 to db7 mpu bus h cs1b cs2 rs e rw db0 to db7 6800 - series l cs1b cs2 rs /rd /wr db0 to db7 8080 - series table 10 . parallel data transfer common 6800 - series 8080 - series rs e_rdb (e) rw_wrb (rw) e_rdb (/rd) rw_wrb (/wr) description h h h l h display data read out h h l h l display data write l h h l h register status read l h l h l writes to internal register (i nstruction)
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 1.5 S6B0725A 14 cs1b cs2 rs rw e db command write data w rite status read data read figure 2 - 1. 6800 - series mpu interface protocol (ps= ? h ? , c68= ? h ? ) cs1b cs2 rs /wr /rd db command write data w rite status read data read figure 2 - 2. 8080 - series mpu interface protocol (ps= ? h ? , c68= ? l ? )
S6B0725A spec . ver. 1.5 104 seg / 65 com driver & controller for stn lcd 15 serial interface (ps = "l") when the S6B0725A i s active (cs1b= ? l ?, cs2= ? h ? ), serial data (db7) and serial clock (db6) inputs are enabled. and not active, the internal 8 - bit shift register and the 3 - bit counter are reset. the display data/command indication may be controlled either via software or the r egister select (rs) pin, based on the setting of c68. when the rs pin is used (ps = ? h ? ), data is display data when rs is high, and command data when rs is low. when rs is not used (c68 = ? l ? ), the lcd driver will receive command from mpu by default. if me ssages on the data pin are data rather than command, m p u should send data direction command (1 0000 000) to control the data direction and then one more command to define the number of data bytes will be write. after these two continuous commands are sending , the following messages will be data rather than command. serial data can be read on the rising edge of serial clock going into db6 and processed as 8 - bit parallel data on the eighth serial clock. and the ddram column address pointer will be increased by one automatically. the next bytes after the display data string is handled as command data. s erial data can be read on the rising edge of serial clock going into db6 and processed as 8 - bit parallel data on the eighth serial clock . since the clock signal ( db6) is easy to be affected by the external noise caused by the line length, the operation check on the actual machine is recommended. t he serial interface type is selected by setting c68 as shown in table 11. table 11 . parallel / serial interface mode ser ial mode ps c68 chip select register select serial data / clock input 4 pin spi serial mode l h cs1b, cs2 rs pin db7 / db6 3 pin spi serial mode l l cs1b, cs2 software db7 / db6 4 pin spi serial interface (ps = "l" , c68 = " h ") in 4 - pin serial interfac e mode, rs pin is used for indicating whether serial data input is display or instruction data. d ata is display data when rs is high and instruction data when rs is low. cs1b cs2 sid sclk rs db6 db7 db0 db1 db2 db3 db4 db5 db6 db7 figure 3 . 4 pin spi s erial inter face timing (rs used)
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 1.5 S6B0725A 16 3 pin - spi interface (ps = "l" , c68 = " l ") in 3 - pin spi interface mode, the pre - defined instruction called display data length, is used to indicate whether serial data input is display or instruction data instead of rs pin. the data i s handled as instruction data until the display data length instruction is issued. this display data length instruction consists of two bytes instruction. the first byte instruction enables the next instruction to be valid, and the data of the second byte indicates that a specified number of display data bytes (1 to 256) are to be transmitted. the next byte after the display data string is handled as instruction data. for details, refers to figure 4. sclk cs1b / cs2 829 830 831 ~ ~ ~ ~ 0 0 1 7 8 ~ ~ 15 ~ ~ 23 sid msb data in page lsb ddc no. of data 3 byte (1) 2 byte (2) 104 byte 0 (1) set page and column address. set page address : 1 0 1 1 p3 p2 p1 p0 set column address msb : 0 0 0 1 0 y6 y5 y4 set column address lsb : 0 0 0 0 y3 y2 y1 y0 (2) set ddc(data direction command) and no. of data bytes. set data direction command( for spi mode only): 1 0 0 0 0 0 0 0 set no. of data bytes(ddl) : d7 d6 d5 d4 d3d2d1d0 figure 4 . 3 pin spi timing (rs is not used) this command is used in 3 - pin spi mode only. it will be two continuous commands, the first byte control s the data direction and inform s the lcd driver the second byte will be number of data bytes will be write. aft er these two commands sending out, the following messages will be data. if data is stopped in transmitting, i t i s not valid data. new d ata will be transferred serially with most significant bit first. *notes: - in spite of transmission of d ata, if cs1 b will be disable, state terminates abnormally. next state is initialized. - the number of writing display data = ddl register value + 1 busy flag the busy flag indicates whether the S6B0725A is operating or not. when db7 is ?h? in read status operati on, this device is in busy status and will accept only read status instruction. if the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the mpu performance.
S6B0725A spec . ver. 1.5 104 seg / 65 com driver & controller for stn lcd 17 data transfer the S6B0725A uses bus holder and internal data bus for data transfer with the mpu. when writing data from the mpu to on - chip ram, data is automatically transferred from the bus holder to the ram as shown in figure 5 . and when reading data from on - chip ram to the mpu, the data f or the initial read cycle is stored in the bus holder (dummy read) and the mpu reads this stored data from bus holder for the next data read cycle as shown in figure 6 . this means that a dummy read cycle must be inserted between each pair of address sets w hen a sequence of address sets is executed. t herefore, the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data. rs /wr db0 to db7 n d(n) d(n+1) d(n+2) d(n+3) internal signals mpu signals /wr bus holder column address n n+1 n+2 n+3 n d(n) d(n+1) d(n+2) d(n+3) figure 5 . write timing rs /wr /rd db0 to db7 n mpu signals dummy d(n) d(n+1) internal signals /wr /rd bus holder column address n d(n) d(n+1) d(n+2) n n+1 n+2 n+3 d(n+2) figure 6 . read timing
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 1.5 S6B0725A 18 display data ram (dd ram) the display data ram stores pixel data for the lcd. it is 65 - row by 1 04 - column addressable array. each pixel can b e selected when the page and column addresses are specified. the 65 rows are divided into 8 pages of 8 lines and the 9 th page with a single line (db0 only). data is read from or written to the 8 lines of each page directly through db0 to db7. the display d ata of db0 to db7 from the microprocessor correspond to the lcd common lines as shown in figure 7 . the microprocessor can read from and write to ram through the i/o buffer. since the lcd controller operates independently, data can be written into ram at th e same time as data is being displayed without causing the lcd flicker. com 0 - - com 1 - - com 2 - - com 3 - - com 4 - - db0 0 0 1 - - 0 db1 1 0 0 - - 1 db2 0 1 1 - - 0 db3 1 0 1 - - 0 db4 0 0 0 - - 1 display data ram lcd display figure 7 . ram - to - lcd data transfer page address circuit this circuit is for providing a page address to display data ram shown in f igure 9 . it incorporates 4 - bit page address register changed by only the ?set page? instruction. page address 8 (db3 is ?h?, but db2, db1 and db0 are ?l?) is a special ram area for the icons and display data db0 is only valid. when page address is above 8, it is impossible to access to on - chip ram. line address circuit this circuit assigns ddram a line address corresponding to the first line (com 0 ) of the display. therefore, by setting line address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on - chip ram as shown in figure 9 . it incorporates 6 - bit line address register changed by only the initial display line instruction and 6 - bit counter circuit. at the beginning of each lcd frame, the conten ts of register are copied to the line counter which is increased by cl signal and generates the line address for transferring the 1 04 - bit ram data to the display data latch circuit. however, display data of icons are not scrolled because the mpu cannot acc ess line address of icons.
S6B0725A spec . ver. 1.5 104 seg / 65 com driver & controller for stn lcd 19 column address circuit column address circuit has a 7 - bit preset counter that provides column address to the display data ram as shown in figure 9 . when set column address msb / lsb instruction is issued, 7 - bit [y 6 :y0] is update d. and, since this address is increased by 1 each a read or write data instruction, microprocessor can access the display data continuously. however, the counter is not incre as ed and locked if a non - existing address above 67 h. it is unlocked if a column ad dress is set again by set column address msb/lsb instruction. and t he column address counter is independent of page address register. adc select instruction makes it possible to invert the relationship between the column address and the segment outputs. it is necessary to rewrite the display data on built - in ram after issuing adc select instruction. refer to the following figure 8 . seg output seg 0 seg 1 seg 2 seg 3 ... ... seg 100 seg 101 seg 102 seg 103 column address [y 7 :y0] 00h 01h 02h 03h ... ... 64 h 65 h 66 h 67 h display data 1 0 1 0 1 1 0 0 lcd panel display ( adc = 0 ) ... ... lcd panel display ( adc = 1 ) ... ... figure 8 . the relationship b etween t he column address a nd t he segment outputs segment con trol circuit this circuit controls the display data by the display on / off, reverse display on / off and entire display on / off instructions without changing the data in the display data ram.
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 1.5 S6B0725A 20 start 1/55 duty page0 page2 page1 page4 page3 page6 page5 page7 page8 line address com output page address db3 db0 db1 db2 data - - - - - - - - - - seg103 seg102 seg1 seg0 seg101 seg100 seg99 seg98 seg2 seg3 seg4 seg5 - - - - - adc=1 adc=0 column address lcd output db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 00h 08h 07h 06h 05h 04h 03h 02h 01h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 18h 17h 16h 15h 14h 13h 12h 11h 19h 1ah 1bh 1ch 1dh 1eh 1fh 20h 28h 27h 26h 25h 24h 23h 22h 21h 29h 2ah 2bh 2ch 2dh 2eh 2fh 30h 38h 37h 36h 35h 34h 33h 32h 31h 39h 3ah 3bh 3ch 3dh 3eh 3fh coms 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1/49 duty 1/33 duty com0 67 65 63 64 62 00 - 02 04 03 05 05 04 03 01 02 00 62 63 64 66 65 67 01 66 when the initial display line address is 1c[hex] com9 com8 com7 com6 com5 com3 com4 com2 com1 com10 com19 com18 com17 com16 com15 com13 com14 com12 com11 com20 com29 com28 com27 com26 com25 com23 com24 com22 com21 com30 com39 com38 com37 com36 com35 com33 com34 com32 com31 com40 com49 com48 com47 com46 com45 com43 com44 com42 com41 com50 com59 com58 com57 com56 com55 com53 com54 com52 com51 com60 com63 com62 com61 figure 9 . display data ram map
S6B0725A spec . ver. 1.5 104 seg / 65 com driver & controller for stn lcd 21 lcd display circuits oscillator this is completely on - chip oscillator and its frequency is nearly independent of v dd . this oscillator signal is used in display timing generation circuit. display timing generator circuit this circ uit generates some signals to be used for displaying lcd. the display clock, cl generated by oscillation clock, generates a clock to the line counter and a latch signal to the display data latch. the line address of on - chip ram is generated in synchronizat ion with the display clock (cl) and the 1 04 - bit display data is latched by the display data latch circuit in synchronization with the display clock. the display data which is read to the lcd driver is completely independent of the access to the display dat a ram from the microprocessor. the lcd ac signal, fr is generated from the display clock. 2 - frame ac driver waveform s with internal timing signal are shown in figure 10 .
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 1.5 S6B0725A 22 com0 vlcd v1 v2 v3 v4 v ss com1 vlcd v1 v2 v3 v4 v ss vlcd v1 v2 v3 v4 v ss segn 64 65 1 2 3 4 5 6 7 8 9 10 11 12 58 59 60 61 62 63 64 65 1 2 3 4 5 6 cl fr figure 10 . 2 - frame ac driving waveform ( d uty ratio = 1/ 6 5) common output control circuit this circuit controls the relationship between the number of common output and specified duty ratio. shl select instruction specifies the scanning direction of the common output pins . table 12. the relationship between du ty ratio and common output common o utput p ins duty shl com [0:15] com [16:23] com [24:26] com [27:36] com [37:39] com [40:47] com [48:63] coms 0 com[0:15] *nc com[16:31] 1/33 1 com[31:16] *nc com[15:0] coms 0 com[0:23] *nc com[24:47] 1/49 1 com[47:24] *nc com[23:0] coms 0 com[0:26] *nc com[27:53 ] 1/55 1 com[53:27] *nc com[26:0] coms 0 com[0:63] 1/65 1 com[63:0] coms *nc: no connection
S6B0725A spec . ver. 1.5 104 seg / 65 com driver & controller for stn lcd 23 lcd driver circuit s this driver circuit is configured by 66 - c hannel (including 2 coms channels) common driver and 1 04 - channel segment driver. this lcd panel driver voltage depends on the combination of display data and fr signal. com 0 com 1 com 2 com 3 com 4 com 5 com 6 com 7 com 8 com 9 com1 0 com1 1 com1 2 com1 3 com1 4 com 15 s e g 4 s e g 3 s e g 2 s e g 1 s e g 0 seg 2 seg 1 seg 0 com 2 com 0 com 1 f r v lcd v1 v2 v3 v4 v ss v lcd v1 v2 v3 v4 v ss v lcd v1 v2 v3 v4 v ss v lcd v1 v2 v3 v4 v ss v lcd v1 v2 v3 v4 v ss v lcd v1 v2 v3 v4 v ss v dd v ss figure 11 . segment and common timing
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 1.5 S6B0725A 24 power supply circuit s the power supply circuits generate the vo ltage levels necessary to drive liquid crystal driver circuits with low - power consumption and the fewest components. there are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. they are controlled by power control instr uction. for details, refers to ? instruction description ? . voltage converter circuits these circuits boost up the electric potential between vci and v ss to 3 or 4 times toward positive side . vout = 3 vci v ss vci vci dcdc4b vout = 4 vci v ss vci vci vdd vdd vci dcdc4b vci vdd v ss figure 12 . three times boosting circuit figure 13 . four times boosting circuit * the vci voltage range must be set so that the vout (voltage converter output) does not exceed the absolute maximum rating value
S6B0725A spec . ver. 1.5 104 seg / 65 com driver & controller for stn lcd 25 voltage reg ulator circuits the function of the internal voltage regulator circuits is to determine liquid crystal operating voltage, v lcd , by adjusting resistors, ra and rb, within the range of |v lcd | < | vout |. because vout is the operating voltage of operational - amp lifier circuits shown in figure 14 , it is necessary to be applied internally. for the eq. 1, we determine v lcd by ra, rb and v ev . the ra and rb are connected internally or externally by intrs pin. and v ev called the voltage of electronic volume is determi ned by eq. 2, where the parameter a is the value selected by instruction, "set reference voltage register", within the range 0 to 63. v ref voltage at ta = 25 c is shown in table 13 . rb v lcd = ( 1 + ? ? ? ? ) x v ev [v] ------ ( eq. 1 ) ra (63 - a ) v ev = ( 1 - ? ? ? ? ? ? ) x v ref [v] ------ ( eq. 2 ) 162 table 13. v ref voltage at ta = 25 c ref temp. coefficient v ref [v] h - 0.05% / c 2.1 l external i nput vext tab le 14. electronic contrast control register (64 steps) s v5 s v4 s v3 s v2 s v1 s v0 reference voltage p arameter ( a ) vlcd contrast 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : : : : : : : 1 0 0 0 0 0 32 ( d efault) : : : : : : : : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63 minimum : : : : : maximum low : : : : : high
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 1.5 S6B0725A 26 v ev gnd ra rb v ss vr v lcd vout + - v ref v ext intrs inside chip ref figure 14 . internal v oltage r egulator c ircuit
S6B0725A spec . ver. 1.5 104 seg / 65 com driver & controller for stn lcd 27 in case of using internal resistors, ra and rb (intrs = "h") when intrs pin is ?h?, resistor ra is connected internally between vr pin and v ss , and rb is connected between v lcd and vr. we determine v lcd by two instructions, "regulator resistor select" and "set reference voltage". table 15 . internal rb / ra ratio depending on 3 - bit data (r2 r1 r0) 3 - bit data settings (r2 r1 r0) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 + (rb / ra) 3.0 3.5 4.0 4.5 5.0 5.5 not available not available the following figure shows v lcd voltage measured by adjusting internal regulator re s ist o r ratio (rb / ra) and 6 - bit electronic volume registers for each temperature coefficient at ta = 25 c. 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 0 8 16 24 32 40 48 56 electronic volume level v0 [v] (1 0 1) (1 0 0) (0 1 1) (0 1 0) (0 0 1) (0 0 0) figure 15 . electronic volume level
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 1.5 S6B0725A 28 in case of using external resistors, ra and rb (intrs = "l") when intrs pin is ?l?, it is necessary to c onnect external regulator resistor ra between vr and v ss , and rb between v lcd and vr. example: for the following requirements 1. lcd driver voltage, v lcd = 6 v 2. 6 - bit reference voltage register = (1, 0, 0, 0, 0, 0) 3. m aximum current flowing ra, rb = 1 ua from eq. 1 rb 6 = ( 1 + ? ? ? ) x v ev [v] ------ ( eq. 3 ) ra from eq. 2 (63 - 32) v ev = ( 1 - ? ? ? ? ? ? ) x 2.1 @ 1. 698 [v] ------ ( eq. 4 ) 162 from requiremen t 3. 6 ? ? ? ? ? ? = 1 [ua] ------ ( eq. 5 ) ra + rb from equations eq. 3, 4 and 5 ra @ 1. 698 [m w ] rb @ 4 . 302 [m w ] the following table shows the range of v lcd depending on the above requirements. table 16. v lcd d epending on electronic volu me l evel electronic volume level 0 ....... 32 ....... 63 v lcd 4.53 ....... 6 .00 ....... 7 . 42
S6B0725A spec . ver. 1.5 104 seg / 65 com driver & controller for stn lcd 29 voltage follower circuits vlcd voltage is resistively divided into four voltage levels (v1, v2, v3, v4), and those output impedance are converted by the volt age follower for increasing drive capability. the following table shows the relationship between v1 to v4 level and each duty ratio. table 17. the relationship between v1 to v4 l evel and duty ratio duty r atio duty1 duty0 lcd bias v1 v2 v3 v4 1/5 (4/5) v lcd (3 / 5) vlcd ( 2/ 5) v lcd ( 1/ 5) v lcd 1/33 l l 1/6 (5/6) v lcd (4 / 6) vlcd ( 2/ 6) vlcd ( 1/ 6) vlcd 1/6 (5/6) vlcd (4 / 6) vlcd ( 2/ 6) vlcd ( 1/ 6) vlcd 1/49 l h 1/8 (7/8) vlcd (6 / 8) vlcd ( 2/ 8) vlcd ( 1/ 8) vlcd 1/6 (5/6) vlcd (4 / 6) vlcd ( 2/ 6) vlcd ( 1/ 6) vlcd 1/55 h l 1/8 (7/8) vlcd (6 / 8) vlcd ( 2/ 8) vlcd ( 1/ 8) vlcd 1/ 7 (6/7) vlcd (5 / 7) vlcd ( 2/ 7) vlcd ( 1/ 7) vlcd 1/65 h h 1/9 (8/9) vlcd (7 / 9) vlcd ( 2/ 9) vlcd ( 1/ 9) vlcd high p ower m ode the power supply circuit equipped in the S6B0725A for lcd drive has very low power consumption (in normal mode: hpmb = ? h ? ). if use for lcd panels with large loads, this low - power power supply may cause display quality to degrade. when this occurs, setting the hpmb pin to ? l ? (high power mode) can improve the quality of th e display.
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 1.5 S6B0725A 30 reset circuit setting resetb to ?l? or reset instruction can initialize internal function. when resetb becomes ?l?, the initialized driver has following states . display on / off: off entire display on / off: off (normal) adc select: off (nor mal) reverse display on / off: off (normal) power control register (vc, vr, vf) = (0, 0, 0) serial interface internal register data clear lcd bias ratio: 1/ 9 (1/65 d uty), 1/8 (1/55 d uty), 1/8 (1/49 d uty), 1 /6 (1/33 d uty) on - chip oscillator off power save r elease r ead - m odify - write : off shl select: off (normal) static indicator mode: off static indicator register: (s1, s0) = (0, 0) d isplay start line: 0 (first) column address: 0 page address: 0 regulator resistor select register: (r2, r1, r0) = ( 0 , 1 , 1 ) ref erence voltage set: off reference voltage control register: ( s v5, s v4, s v3, s v2, s v1, s v0) = (1, 0, 0, 0, 0, 0) test mode release when reset instruction is issued, the initialized driver has following states . r ead - m odify - write : off static indicator mode: off static indicator register: (s1, s0) = (0, 0) shl select: 0 d isplay start line: 0 (first) column address: 0 page address: 0 regulator resistor select register: (r2, r1, r0) = ( 0 , 1 , 1 ) reference voltage set: off reference voltage control register: ( s v5 , s v4, s v3, s v2, s v1, s v0) = (1, 0, 0, 0, 0, 0) test mode release while resetb is ?l? or reset instruction is executed, no instruction except read status c ould be accepted. reset status appears at db4. after db4 becomes ?l?, any instruction can be accepte d. resetb must be connected to the reset pin of the mpu, and initialize the mpu and this lsi at the same time. the initialization by resetb is essential before used.
S6B0725A spec . ver. 1.5 104 seg / 65 com driver & controller for stn lcd 31 instruction descript ion table 18 . instruction table : don?t care instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 description display on / off 0 0 1 0 1 0 1 1 1 d on turn on / off lcd panel when d on = 0: display off when d on = 1: display on initial display line 0 0 0 1 s t 5 s t 4 s t 3 s t 2 s t 1 s t 0 specify ddram line for com0 set page address 0 0 1 0 1 1 p3 p2 p1 p0 set page address set column address msb 0 0 0 0 0 1 y6 y5 y4 set column address msb set column address lsb 0 0 0 0 0 0 y3 y2 y1 y0 set column address lsb read status 0 1 busy adc on /off res etb 0 0 0 0 read the internal status w rite display data 1 0 write data write data into ddram read display data 1 1 read data read data from ddram adc select 0 0 1 0 1 0 0 0 0 adc select seg output direction when adc = 0 : normal direction (seg0 ? seg103) when a dc = 1 : reverse direction (seg103 ? seg0) reverse display on / off 0 0 1 0 1 0 0 1 1 rev select normal / reverse display when rev = 0 : normal display when rev = 1 : reverse display entire display on / off 0 0 1 0 1 0 0 1 0 eon select normal/ entire display on when eon = 0 : normal display. when eon = 1 : entire display on lcd bias select 0 0 1 0 1 0 0 0 1 bias select lcd bias set modify - read 0 0 1 1 1 0 0 0 0 0 set modify - read mode reset modify - read 0 0 1 1 1 0 1 1 1 0 release modify - read mode r eset 0 0 1 1 1 0 0 0 1 0 initialize the internal functions shl select 0 0 1 1 0 0 shl select com output direction when shl = 0 : normal direction (com0 ? com63) when shl = 1: reverse direction (com63 ? com0) power control 0 0 0 0 1 0 1 vc vr vf control power circuit operation regulator resistor select 0 0 0 0 1 0 0 r2 r1 r0 select internal resistance ratio of the regulator resistor set r eference v oltage m ode 0 0 1 0 0 0 0 0 0 1 set r eference v oltage m ode set r eference v oltage r egister 0 0 s v5 s v4 s v3 s v2 s v1 s v0 set r eference v oltage r egister set static indicator mode 0 0 1 0 1 0 1 1 0 sm set static indicator mode set static indicator register 0 0 s1 s0 set static indicator register x x 1 0 0 0 0 0 0 0 set data direction & display data lengt h (ddl) x x d7 d6 d5 d4 d3 d2 d1 d0 2 - byte instruction to specify the number of data bytes (spi mode) power s ave - - - - - - - - - - compound instruction of display off and entire display on
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 1.5 S6B0725A 32 table 18 . instruction table (continued ) : don?t care instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 description nop 0 0 1 1 1 0 0 0 1 1 non - operation command test i nstruction_1 0 0 1 1 1 1 don ? t use this instruction test i nstruction_2 0 0 1 0 0 1 don ? t use this instruct ion
S6B0725A spec . ver. 1.5 104 seg / 65 com driver & controller for stn lcd 33 display on / off turns the display on or off rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 1 1 d on d on = 1: display on d on = 0: display off initial display line sets the line address of display ram to determine the initial displ ay line . the ram display data is displayed at the top row (com 0 when shl = l, com63 when shl = h ) of lcd panel. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 s t 5 s t 4 s t 3 s t 2 s t 1 s t 0 s t 5 s t 4 s t 3 s t 2 s t 1 s t 0 line address 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63 s et page address sets the page address of display data ram from the microprocessor into the page address register. any ram data bit can be accessed when its page address and column address are specified. al ong with the column address, the page address defines the address of the display ram to write or read display data. changing the page address doesn't effect to the display status. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 1 p3 p2 p1 p0 p3 p2 p1 p 0 p age 0 0 0 0 0 0 0 0 1 1 : : : : : 0 1 1 1 7 1 0 0 0 8
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 1.5 S6B0725A 34 set column address sets the column address of display ram from the microprocessor into the column address register. along with the column address, the column address defines the address of th e display ram to write or read display data. when the microprocessor reads or writes display data to or from display ram, column addresses are automatically incre as ed. set column address msb rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 x y6 y5 y4 se t column address lsb rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 y3 y2 y1 y0 y6 y5 y4 y3 y2 y1 y0 c olumn address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : 1 1 0 0 1 1 0 102 1 1 0 0 1 1 1 103 read status indicates the internal status of the S6B0725A rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 1 busy adc on / off res etb 0 0 0 0 flag description busy the device is busy when internal operation or reset. any instruction is rejected until busy goes low. 0: chip is active, 1: chip is being b usy adc indicates the relationship between ram column address and segment driver. 0: reverse direction (seg 103 ? seg 0 ), 1: normal direction (seg 0 ? seg 103 ) on / off indicates display on / off status. 0: display on, 1: display off res etb indicates the in itialization is in progress by resetb signal. 0: chip is active, 1: chip is being reset
S6B0725A spec . ver. 1.5 104 seg / 65 com driver & controller for stn lcd 35 write display data 8 - bit data of display data from the microprocessor can be written to the ram location specified by the column address and page address. the column address is incre as ed by 1 automatically so that the microprocessor can continuously write data to the addressed page. rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 0 write data data write set column address set page address optional status column = column + 1 no yes data write continue ? dummy data read set column address set page address optional status column = column + 1 no yes data read continue ? data read column = column + 1 figure 16 . sequence for writing display data figure 17 . sequence for reading display data read display data 8 - bit data from display data ram specified by the column address and page address can be read by this instruction. as the column address is incre as ed by 1 automatically after each t his instruction, the microprocessor can continuously read data from the addressed page. a dummy read is required after loading an address into the column address register. display data cannot be read through the serial interface. rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 1 read data adc select (s egment driver direction select) changes the relationship between ram column address and segment driver. the direction of segment driver output pins can be reversed by software. this makes ic layout flexible in lcd m odule assembly. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 0 0 adc adc = 0: normal direction (seg 0 ? seg 103 ) adc = 1: reverse direction (seg 103 ? seg 0 )
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 1.5 S6B0725A 36 reverse display on / off reverses the display status on lcd panel without rewriting the cont ents of the display data ram. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 1 rev rev ram bit data = ?1? ram bit data = ?0? 0 (normal) lcd pixel is illuminated lcd pixel is not illuminated 1 (reverse) lcd pixel is not illuminated lcd pixel is illuminated entire display on / off forces the whole lcd points to be turned on regardless of the contents of the display data ram. at this time, the contents of the display data ram are held. this instruction has priority over the reverse display on/off instruction. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 0 eon eon = 0: normal di splay eon = 1: e ntire d isplay o n select lcd bias selects lcd bias ratio of the voltage required for driving the lcd. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 0 1 bias lcd bias d uty r atio d uty 1 d uty0 b ias = 0 b ias = 1 1/33 0 0 1/ 6 1/5 1/49 0 1 1/ 8 1/6 1/55 1 0 1/8 1/6 1/65 1 1 1/ 9 1/7 set modify - read this instruction stops the automatic increment of the column address by the read display dat a instruction, but the column address is still increased by the write display data instruction. and it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. this mode is canceled by the reset modify - read instruction. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 0 0
S6B0725A spec . ver. 1.5 104 seg / 65 com driver & controller for stn lcd 37 reset modify - read this instruction cancels the modify - read mode, and makes the column address return to its initial value just before the set modify - read instructio n is started. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 1 1 1 0 set modify- r ead reset modify- r ead set page address data p rocess no yes change c omplete ? set column address (n) dummy r ead data r ead data w rite return c olumn a ddress (n) figure 18 . sequence for cursor display reset this instruction resets initial display line, column address, page address, and common output status select to their initial status, but do es not affect the contents of display data ram. this instruction cannot initialize the lcd power supply , which is initialized by the resetb pin. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 1 0
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 1.5 S6B0725A 38 shl select (c ommon output mode select ) com output scanning direction is selected by this instruction which determines the lcd driver output status. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 0 0 shl : don ? t care shl = 0: normal direction (com 0 ? com 63 ) shl = 1: reverse direction (com 63 ? com 0 ) power control selects one of eight power circuit functions by using 3 - bit register. an external power supply and part of internal power sup ply functions can be used simultaneously. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 1 vc vr vf vc vr vf status of internal power supply circuits 0 1 internal voltage converter circuit is off internal voltage converter circuit is on 0 1 int ernal voltage regulator circuit is off internal voltage regulator circuit is on 0 1 internal voltage follower circuit is off internal voltage follower circuit is on regulator resistor select selects resistance ratio of the internal resistor used in the internal voltage regulator. see voltage regulator section in power supply circuit. refer to the table 15 . rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 0 r2 r1 r0 r2 r1 r0 (1 + rb / ra) ratio 0 0 0 3.0 0 0 1 3.5 0 1 0 4.0 0 1 1 4. 5 (default) 1 0 0 5.0 1 0 1 5.5 1 1 0 not available 1 1 1 not available
S6B0725A spec . ver. 1.5 104 seg / 65 com driver & controller for stn lcd 39 r eference v oltage s elect consists of 2 - byte instruction. the 1 st instruction sets reference voltage mode , the 2 nd one updates the contents of reference vol tage register. after second instruction, reference voltage m ode is released. the 1 st instruction : set reference voltage select m ode rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 0 0 0 0 1 the 2 nd instruction : set reference voltage r egister rs rw db7 db6 db5 db4 db3 db2 d b1 db0 0 0 sv5 s v4 s v3 s v2 s v1 s v0 s v5 s v4 s v3 s v2 s v1 s v0 reference voltage p arameter ( a ) v0 contrast 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : : : : : : : 1 0 0 0 0 0 32 ( d efa ult) : : : : : : : : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63 minimum : : : : : maximum low : : : : : high 2 nd instruction for register setting setting r eference v oltage end 1 st instruction for mode setting setting r eference v oltage start figure 19 . sequence for setting the r eference v oltage
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 1.5 S6B0725A 40 set static indicator state consists of two bytes instruction. the first byte instruction (set stat ic indicator mode) enables the second byte instruction (set static indicator register) to be valid. the first byte sets the static indicator on/off. when it is on, the second byte updates the contents of static indicator register without issuing any other instruction and this static indicator state is released after setting the data of indicator register. the 1 st instruction: set static indicator mode (on / off) rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 1 0 sm sm = 0: static indicator off sm = 1: static indicator on the 2 nd instruction: set static indicator register rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 s1 s0 s1 s0 status of static indicator output 0 0 off 0 1 on (about 1 second blinking) 1 0 on (about 0.5 second blinking) 1 1 on (always on)
S6B0725A spec . ver. 1.5 104 seg / 65 com driver & controller for stn lcd 41 set data direction & dis play data length (3 - pin spi mode) consists of two bytes instruction. this command is used in 3 - pin spi mode only (ps = ? l ? and c68 = ? l ? ) . it will be two continuous commands, the first byte control the data direction (write mode only) and inform the lcd driver the second byte will be number of data bytes will be write. when rs is not used, the display data length instruction is used to indicate that a specified number of display data bytes are to be transmit ted. the next byte after the display data string is handled as command data. the 1 st instruction: set data direction (only write mode) rs rw db7 db6 db5 db4 db3 db2 db1 db0 x x 1 0 0 0 0 0 0 0 the 2 nd instruction: set display data length (ddl) registe r rs rw db7 db6 db5 db4 db3 db2 db1 db0 x x d7 d6 d5 d4 d3 d2 d1 d 0 d7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 display data length 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 2 0 0 0 0 0 0 1 0 3 : : : : : : : : : 1 1 1 1 1 1 0 1 254 1 1 1 1 1 1 1 0 255 1 1 1 1 1 1 1 1 2 56 nop non - operation i nstruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 1 1 t est i nstruction (t est i nstruction _1 & t est i nstruction_ 2) these are the instruction for ic chip testing. please do not use it. if the test instruction is used by accident, it can be cleared by applying ? 0 ? signal to the resetb input pin or the reset instruction. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 1 0 0 1 0 0 1
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 1.5 S6B0725A 42 power save ( compound insrtuction ) if th e e ntire d isplay on / off inst ruction is issued during the display off state, S6B0725A enters the power save status to reduce the power consumption to the static power consumption value. according to the status of static indicator mode, power save is entered to one mode of sleep and st andby mode. when static indicator mode is on, standby mode is issued. when off, sleep mode is issued. power s ave mode is released by the e ntire d isplay off instruction. sleep mode [oscillator c ircuit: o ff] [lcd power s upply c ircuit: off] [all com / seg o utputs: vss] [consumption c urrent: <2ua] power save off (compound instruction) [entire display o ff ] [static indicator on] 2 b ytes c ommand power save (compound instruction) [display off] [entire display on] static indicator off static indicator on standby mode [oscillator c ircuit: on] [lcd power s upply c ircuit: off] [all com / seg o utputs: vss] [consumption c urrent: <10ua] power save off [entire display o ff ] release sleep mode release standby mode figure 20. power save (compound instruction) - sleep mode thi s stops all operations in the lcd display system, and as long as there are no access from the mpu, the consumption current is reduced to a value near the static current. the internal modes during sleep mode are as follows: a. the oscillator circuit and the lcd power supply circuit are halted. b. all liquid crystal drive circuits are halted, and the segment and common outputs go to the v ss level. - standby mode the duty lcd display system operations are halted and only the static drive system for the indi cator continues to operate, providing the minimum required consumption current for the static drive. the internal modes are in the following states during standby mode. a. the lcd power supply circuits are halted. the oscillator circuit continues to oper ate. b. the duty drive system liquid crystal drive circuits are halted and the segment and common outputs go to the v ss level. the static drive system does not operate. when a reset command is performed while in standby mode, the system enters slee p mode.
S6B0725A spec . ver. 1.5 104 seg / 65 com driver & controller for stn lcd 43 r eferential instruction setup flow (1) end of initialization waiting for stabilizing the lcd power levels user application setup by internal instructions [adc select] [shl select] [lcd bias select] start of initialization resetb pin = ? h ? waiting for stabilizing the power power o n (v dd - v ss ) keeping the resetb pin = ? l ? user system setup by external pins user lcd p ower setup by internal instructions [voltage converter on] user lcd p ower setup by internal instructions [voltage regulator on] user lcd p ower setup by internal instructions [voltage follower on] user lcd p ower setup by internal instructions [regulator r esistor s elect] [reference voltage r egister s et] waiting for 3 25ms waiting for 3 1ms figure 21 . initializing with the b uilt - in p ower s upply c ircuits
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 1.5 S6B0725A 44 r eferential instruction setup flow (2) end of initialization write initial display data display data ram addressing by instruction [initial display line] [set page address] [set column address] end of data display turn display on by instruction [display o n / off : don = 1 ] figure 22 . data d isplaying
S6B0725A spec . ver. 1.5 104 seg / 65 com driver & controller for stn lcd 45 r eferential instr uction setup flow (3) turn display off by instruction [display o ff ] optional status power off (v dd - v ss ) turn off the voltage follower by internal instructions [voltage follower o ff ] turn off the voltage regulator by internal instructions [voltage regulator o ff ] turn off the voltage converter by internal instructions [voltage converter o ff ] waiting for 3 50ms waiting for 3 1ms waiting for 3 1ms figure 23 . power o ff
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 1.5 S6B0725A 46 specifications absolute maximum rat ings table 19. absolute maximum ratings parameter symbol rating unit v dd - 0.3 to + 7 .0 v supply voltage range v lcd - 0.3 to + 13 .0 v input vol tage range v in - 0.3 to v dd + 0.3 v operating temperature range t opr - 40 to +85 c storage temperature range t str - 55 to +125 c notes: 1. v dd and v lcd are based on v ss = 0v. 2. voltages v lcd 3 v1 3 v2 3 v3 3 v4 3 v ss must always be satisfied. 3. i f supply voltage exceeds its absolute maximum range, this lsi may be damaged permanently. it is desirable to use this lsi under electrical characteristic conditions during general operation. otherwise, this lsi may malfunction or reduced lsi reliabil ity may result.
S6B0725A spec . ver. 1.5 104 seg / 65 com driver & controller for stn lcd 47 dc characteristics table 20. dc characteristics (v ss = 0v, v dd = 2.4 to 3.6v, ta = - 40 to 85 c) item symbol condition min. typ. max. unit pin used operating voltage (1) v dd 2.4 - 3.6 v vdd *1 lcd power voltage (2) v lcd 4.5 - 9.0 v v lcd *2 high v ih 0.8v dd - v dd input voltage low v il v ss - 0.2v dd v *3 high v oh i oh = - 0.5ma 0.8v dd - v dd output voltage low v ol i ol = 0.5ma v ss - 0.2v dd v *4 input leakage current i il v in = v dd or v ss - 1.0 - + 1.0 m a * 5 output leakage current i o z v in = v dd or v ss - 3.0 - + 3.0 m a * 6 lcd driver on resistance r on ta = 25 c, v0 = 8v - 2.0 3.0 k w segn comn * 7 internal f osc 32.7 43.6 54.5 oscillator frequency external f cl ta = 25 c duty ratio = 1/65 4.09 5.45 6.81 khz cl *8 3 2.4 - 3.6 voltage converter i nput voltage vci 4 2.4 - 3.0 v vci reference voltage v ref ta = 25 c - 0.05%/ c 2.04 2.1 2.16 v * 9
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 1.5 S6B0725A 48 dynamic current consumption when t he b uilt - in p ower c ircuit is on (at o perate m ode) (ta = 25 c ) item symbol con dition min. typ. max. unit pin used v dd = 3.0 v, (vci = v dd , 3 times boosting ) v0 ? v ss = 7.64 v, 1/65 duty ratio, display pattern off, normal power mode - 120 - m a *1 1 v dd = 3.0 v, (vci = v dd , 3 times boosting ) v0 ? v ss = 7.64 v, 1/65 duty ratio, display pattern checker, normal power mode - 140 - m a *1 1 v dd = 3.0 v, (vci = v dd , 4 times boosting ) v0 ? v ss = 8.40 v, 1/65 duty ratio, display pattern off, normal power mode - 180 - m a *1 1 dynamic current consumption (2) i dd2 v dd = 3.0 v, (vci = v dd , 4 times boosting ) v0 ? v ss = 8.40 v, 1/65 duty ratio, display pattern checker, normal power mode - 200 - m a *1 1 current consumption during power save m ode (ta = 25 c) item symbol condition min. typ. max. unit pin used sleep mode current i dds1 during s leep - - 2 m a standby mode current i dd s 2 during s tandby - - 10 m a
S6B0725A spec . ver. 1.5 104 seg / 65 com driver & controller for stn lcd 49 table 21 . the relationship between oscillation frequency and frame frequency duty ratio item f cl f fr 1/ 65 on - chip oscillator circuit is used f osc ? ? ? ? 8 f osc ? ? ? ? 2 8 65 1/55 on - chip oscillator circuit is used f osc ? ? ? ? 9 f osc ? ? ? ? 2 9 55 1/49 on - chip oscillator circuit is used f osc ? ? ? ? 10 f osc ? ? ? -- ? 2 10 49 1/33 on - chip oscillator circuit is used f osc ? ? ? ? 15 f osc ? ? ? ? 2 15 33 (f osc : oscillation frequenc y, f cl : display clock frequency, f fr : lcd ac signal frequency ) [* remark solves] *1 . though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from the mpu. *2 . in case of externa l power supply is applied. *3 . cs1b, cs2, rs, db0 to db7, e_rdb, rw_wrb, resetb, c68 , ps, intrs, hpm b pins . *4 . db0 to db7, fr, frs, cl pins. *5 . cs1b, cs2, rs, db[7:0], e_rdb, rw_wrb, resetb, c68 , ps, intrs, hpm b pins. *6 . applies when the db[7:0], fr, fr s and cl pins are in high impedance. *7 . resistance value when 0.1[ma] is applied during the on status of the output pin segn or comn. ron = d v / 0.1 [k w ] ( d v: voltage change when 0.1[ma] is applied in the on status.) *8 . see table 21 for the rela tionship between oscillation frequency and frame frequency. * 9. on - chip reference voltage source of the voltage regulator circuit to adjust v lcd . *10,11. applies to the case where the on - chip oscillation circuit is used and no access is made from the mpu. the current consumption, when the built - in power supply circuit is on or off. the current flowing through voltage regulation resistors (ra and rb) is not included. it does not include the current of the lcd panel capaci ty, wiring capacity, etc.
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 1.5 S6B0725A 50 ac characteristics read / write characteristics (8080 - series mpu) t dh80 t od80 t ds80 t acc80 0.9v dd 0.1v dd t pw l 80(r) , t pw l 80(w) t cy80 t ah80 t as80 db 0 to db 7 (write) db 0 to db 7 (read) rd b , wr b cs1b (cs2) rs t pw h 80(r) , t pw h 80(w) ** t pwl80(w) and t pwl80(r) is specified in the overlapped period when cs1b is low (cs2 is high) and wrb(rdb) is low. figure 24. read / write characteristics (8080 - series mpu) (v dd = 2.4 to 3.6v, ta = - 40 to +85 c) item signal symbol min. typ . max. un it remark address setup time address hold time rs t as80 t ah80 0 0 - - ns system cycle time rs t cy80 300 - - ns pulse width (wr b ) rw_wrb t pw l 80 (w) t pw h 80 (w) 60 60 - - ns pulse width (rd b ) e_rdb t pw l 80 (r) t pw h 80 (r) 60 60 - - ns data setup time d ata hold time t ds80 t dh80 40 15 - - ns read access time output disable time db7 to db0 t acc80 t od80 - 10 - 140 100 ns c l = 100 pf note: 1. the input signal rising time and falling time (tr,tf) is specified at 15ns or less. (tr + tf) < ( t cy80 - t pw l 80 (w) - t pw h 80 (w) ) for write, (tr + tf) < ( t cy80 - t pw l 80 (r) - t pw h 80 (r) ) for read
S6B0725A spec . ver. 1.5 104 seg / 65 com driver & controller for stn lcd 51 read / write characteristics (6800 - series microprocessor) t dh68 t od68 t ds68 t acc68 0.9v dd 0.1v dd t pw h 68(r) , t pw h 68(w) t cy68 t ah68 t as68 db 0 to db 7 (write) e cs1b (cs2) rs rw db 0 to db 7 (read) t pw l 68(r) , t pw l 68(w) ** t pwh68(w) and t pwh68(r) is specified in the overlapped period when cs1b is low (cs2 is high) and e is high. figure 25. read / write characteristics (6800 - series microprocessor) (v dd = 2.4 to 3.6 v, ta = - 40 to +85 c) item signal symbol min. typ . max. unit remark address setup time address hold time rs rw t as68 t ah68 0 0 - - ns system cycle time rs t cy68 300 - - ns data setup time data hold time t ds68 t dh68 40 15 - - ns access time output disable time db7 to db0 t acc68 t od68 - 10 - 140 100 ns c l = 100 pf enable pulse width read write e_rdb t pw h 68(r) t pw l 68(r) t pw h 68(w) t pw l 68(w) 120 120 60 60 - - ns note: 1. the input signal rising time and falling time (tr,tf) is specif ied at 15ns or less. (tr + tf) < ( t cy 6 8 ? t pw h68 (w) ? t pw h6 8 (w) ) for write, (tr + tf) < ( t cy80 ? t pw h6 8 (r) ? t pw l6 8 (r) ) for read
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 1.5 S6B0725A 52 serial interface characteristics db7 (sid) db6 (sclk) rs cs1b (cs2) t dhs t dss t whs 0.9v dd 0.1v dd t wls t cys t ahs t ass t chs t css figure 26. serial interface characteristics (v dd = 2.4 to 3.6 v, ta = - 40 to +85 c) item signal symbol min. typ . max. unit remark serial clock cycle sclk high pulse width sclk low pulse width db6 (sclk) t cys t whs t wls 250 100 100 - - - - - - ns address setup time address hold time rs t ass t ahs 15 0 150 - - - - ns data setup time data hold time db7 (sid) t dss t dhs 100 100 - - - - ns cs1b setup time cs1b hold time cs1b t css t chs 150 150 - - - - ns note: 1. the input signal rising time and falling time (tr,tf) is specified at 15ns or less.
S6B0725A spec . ver. 1.5 104 seg / 65 com driver & controller for stn lcd 53 re set input timing resetb t rw internal status t r during reset reset complete figure 27. reset input timing (v dd = 2.4 to 3.6 v, ta = - 40 to +85 c) item signal symbol min. typ . max. unit remark reset low pulse width resetb t rw 1.0 - - m s reset time - t r - - 1.0 m s display control output timing t dfr cl (out) fr figure 28. display control output timing (v dd = 2.4 to 3.6 v, ta = - 40 to +85 c) item signal symbol min. typ . max. unit remark fr d elay t ime fr t dfr - 20 80 ns c l = 50 pf
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 1.5 S6B0725A 54 reference applicatio ns microprocessor i nterface in case of interfacing with 6800 - series (ps = ?h?, c68 = ?h?) db0 to db7 resetb v dd v dd rw e rs cs2 cs1b 6800-series mpu cs1b cs2 rs e_rd b rw_wr b db0 to db7 resetb c68 ps s 6b 07 25 figure 29. i nterfacing with 6800 - series in case of interfacing with 8080 - series (ps = ?h?, c68 = ?l?) db0 to db7 resetb v dd v ss wr b rd b rs cs2 cs1b 8080-series mpu cs1b cs2 rs e_rd b rw_wr b db0 to db7 resetb c68 ps s 6b 07 25 figure 30. i nterfacing wit h 8080 - series
S6B0725A spec . ver. 1.5 104 seg / 65 com driver & controller for stn lcd 55 in case of serial interface with rs pin (ps = ?l?, c68 = ?h ?) open resetb v ss v dd sclk sid rs cs2 cs1b mpu cs1b cs2 rs db7(sid) db6(sclk) resetb db0 to db5 c68 ps s 6b 07 25 figure 31. 4 pin s erial i nterface in case of serial interface with software command (ps = ?l?, c68 = ? l ?) open resetb v ss v ss sclk sid cs2 cs1b mpu cs1b cs2 rs db7(sid) db6(sclk) resetb db0 to db5 c68 ps s 6b 07 25 v ss or v dd figure 32. 3 pin spi s erial i nterface
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 1.5 S6B0725A 56 connections between S6B0725A and lcd pan el single chip structure (1/ 6 5 duty configurations) com 32 : com 6 3 coms coms com 0 : com 3 1 seg 0 ........... seg103 s 6b 07 2 5 (bottom view) ? a x a ? a x a 64 104 pixels com s com 0 : com 31 com3 2 : com6 3 coms seg103 ........... seg 0 s 6b 07 2 5 (top view) ? a x a ? a x a 64 104 pixels figure 33 . shl = 1, adc = 0 figure 34 . shl = 1 , adc = 1 coms com 6 3 : com 32 com 3 1 : com 0 coms seg 0 ........... seg103 s 6b 07 2 5 (top view) coms com 6 3 : com 32 com 3 1 : com 0 coms seg103 ............ seg 0 s 6b 07 2 5 (bottom view) ? a x a ? a x a 64 104 pixels ? a x a ? a x a 64 104 pixels figure 35 . shl = 0 , adc = 0 figure 36 . shl = 0, adc = 1
S6B0725A spec . ver. 1.5 104 seg / 65 com driver & controller for stn lcd 57 single chip structure (1/ 55 duty configurations) com 37 : com 6 3 coms coms com 0 : com 26 seg 0 ........... seg103 s 6b 07 2 5 (bottom view) ? a x a ? a x a 5 4 104 pixels com s com 0 : com 26 com 37 : com 63 coms seg103 ........... seg 0 s 6b 07 2 5 (top view) ? a x a ? a x a 5 4 104 pixels figure 37 . shl = 1, adc = 0 figure 38 . shl = 1, adc = 1 coms com 6 3 : com 37 com 26 : com 0 coms seg 0 ........... seg103 s 6b 07 2 5 (top view) coms com 6 3 : com 37 com 26 : com 0 coms seg103 ............ seg 0 s 6b 07 2 5 (bottom view) ? a x a ? a x a 5 4 104 pixels ? a x a ? a x a 5 4 104 pixels figure 39 . shl = 0 , adc = 0 figure 40 . shl = 0 , adc = 1
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 1.5 S6B0725A 58 single chip st ructure (1/ 49 duty configurations) com 40 : com 6 3 coms coms com 0 : com 23 seg 0 ........... seg103 s 6b 07 2 5 (bottom view) ? a x a ? a x a 48 104 pixels com s com 0 : com 23 com 40 : com6 3 coms seg103 ........... seg 0 s 6b 07 2 5 (top view) ? a x a ? a x a 4 8 104 pixels figure 41 . shl = 1 , adc = 0 figure 42 . shl = 1 , adc = 1 coms com 6 3 : com 40 com 23 : com 0 coms seg 0 ........... seg103 s 6b 07 2 5 (top view) coms com 6 3 : com 40 com 23 : com 0 coms seg103 ............ seg 0 s 6b 07 2 5 (bottom view) ? a x a ? a x a 48 104 pixels ? a x a ? a x a 48 104 pixels figure 43 . shl = 0 , adc = 0 figure 44 . shl = 0 , adc = 1
S6B0725A spec . ver. 1.5 104 seg / 65 com driver & controller for stn lcd 59 single chip structure (1/ 33 duty configurations) com 48 : com 6 3 coms coms com 0 : com 15 seg 0 ........... seg103 s 6b 07 2 5 (bottom view) ? a x a ? a x a 32 104 pixels com s com 0 : com 15 com 48 : com6 3 coms seg103 ........... seg 0 s 6b 07 2 5 (top view) ? a x a ? a x a 32 104 pixels figure 45 . shl = 1, adc = 0 figure 46 . shl = 1, adc = 1 coms com 6 3 : com 48 com 15 : com 0 coms seg 0 ........... seg103 s 6b 07 2 5 (top view) coms com 6 3 : com 48 com 15 : com 0 coms seg103 ............ seg 0 s 6b 07 2 5 (bottom view) ? a x a ? a x a 32 104 pixels ? a x a ? a x a 32 104 pixels figure 47 . shl = 0, adc = 0 figure 48 . shl = 0, adc = 1
104 seg / 65 com drive r & controller for s tn lcd spec. ver. 1.5 S6B0725A 60 S6B0725A application circuit for serial mode n 4 pin spi serial interface lcd panel v lcd v dd vci sclk si d rs cs1b s 6b 07 25a r es etb v ss vcc port4 port3 port1 port0 mpu reset gnd gnd v cc lcd module commons gnd c1 segments com[0:64] seg[0:103] * c1 is greater than 1 m f + - f igure 49. S6B0725A application circuit for 4 pin spi serial interface

▲Up To Search▲

Price & Availability of S6B0725A

	To Download S6B0725A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .